1. Field of the Invention
The invention generally relates to semiconductor processing. More particularly, the invention relates to metallization of sub-micron interconnect features on a substrate.
2. Background of the Related Art
Copper has become a choice metal for filling sub-micron, high aspect ratio interconnect features on substrates as circuit densities increase for the next generation of ultra large scale integration because copper and copper alloys have lower resistivity than aluminum and significantly higher electromigration resistance as compared to aluminum. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increased device speed.
The aspect ratios for the features, i.e., the ratio for the feature height to the feature width, increases with the higher level of integration. Many traditional deposition processes have difficulty filling structures or features having sub-micron width where the aspect ratio exceeds 4:1, and particularly where the ratio exceeds 10:1. Thus, there is a great amount of ongoing effort being directed at the formation of void-free sub-micron features having high aspect ratios.
Despite the desirability of using copper for semiconductor device fabrication, choices of fabrication methods for depositing copper into very high aspect ratio features are limited because common chemical vapor deposition processes and physical vapor deposition processes have provided unsatisfactory results in forming void-free sub-micron features having high aspect ratios. Furthermore, the vapor deposition processes can be costly. As a result, electroplating or electrochemical deposition is becoming an accepted method for copper metallization of interconnect features on semiconductor devices.
Metal electroplating in general is a well known art and can be achieved by a variety of techniques. Present designs of cells for electroplating a metal onto a substrate are generally based on a fountain plater configuration. In the fountain plater configuration, the semiconductor substrate is positioned above a cylindrical electrolyte container with the plating surface facing an opening of the cylindrical electrolyte container. The electrolyte is pumped to flow upwardly and contact the substrate plating surface. The substrate is electrically biased and connected as the cathode of the plating system, and the surfaces to be plated are electrically connected to the cathode power source to provide the electrical current that induces the metal ions in the plating solution to deposit onto the exposed conductive surface of the substrate. An anode is typically disposed in the electrolyte and electrically biased to attract the negatively charged counterparts of the metal ions in the electrolyte. The fountain plater is generally adequate for electroplating large, low aspect ratio features (i.e., larger than micrometer-sized and lower than 1:1 height to width ratio). However, a number of obstacles impair consistent electroplating of copper onto substrates having sub-micron high aspect ratio features.
First, a continuous metal seed layer is essential for conducting the current required to the surfaces to be plated by the electroplating process. When a discontinuity is present in the metal seed layer, the portion of the seed layer that is not electrically connected to the bias power supply does not receive deposition during the electroplating process. Currently practiced physical vapor deposition methods encounters difficulty in forming a continuous, uniform seed layer within a sub-micron high aspect ratio feature. The seed layer tends to become discontinuous on the sidewall surfaces and the bottom surface of the feature because of the difficulty in depositing into the narrow (i.e., nanometer-sized) aperture width of the feature. The discontinuities in the seed layer prevent proper electroplating of metal onto the seed layer, resulting in defective devices on the processed substrate.
Second, it has been difficult to deposit into sub-micron high aspect ratio features without forming voids in the feature because the horizontal electroplated metal growth tends to close off the feature at the aperture opening before the feature has been completely filled, resulting in a void forming within the feature. A void formation in the feature changes the material and operating characteristics of the interconnect feature, such as decreasing electromigration resistance, and typically causes improper operation and premature breakdown of the device. To reduce void formation in a high aspect ratio feature, the upper corners at the feature opening are typically rounded off by an etching process. However, the additional etching step to round-off corners of features increases the processing time for each substrate and reduces throughput of the system. Furthermore, voids may still form within the features during the deposition process even with rounded corners at the feature opening.
Third, currently practiced electroplating methods have not provided consistent electroplating results between sequentially processed substrate in a single run. Also, the material properties of the electroplated metal layer, such as grain size, orientation, reflectivity and resistance, are not sufficiently uniform across the deposited substrate surface of a single substrate when processed with typical electroplating systems.
Therefore, there is a need for a consistent metal electroplating technique to form void-less metal interconnects in sub-micron high aspect ratio features on semiconductor substrates. Particularly, there is a need for a method for preparing a substrate prior to electroplating that overcomes the problems presented by currently practiced seed layers used in electroplating and reduces the formation of defective devices. There is also a need for a method for electroplating a metal into sub-micron high aspect ratio feature that provides consistent electroplating results between sequentially processed substrate and uniform material properties of the electroplated metal layer across the deposited substrate surface on a single substrate.
One aspect of the invention provides a consistent metal electroplating technique to form void-less metal interconnects in sub-micron high aspect ratio features on semiconductor substrates. Another aspect of the invention provides a method for preparing a substrate prior to electroplating that overcomes the problems presented by currently practiced seed layers used in electroplating and reduces the formation of defective devices. Another aspect of the invention provides a method for electroplating a metal into sub-micron high aspect ratio feature that provides consistent electroplating results between sequentially processed substrate and uniform material properties of the electroplated metal layer across the deposited substrate surface on a single substrate.
One embodiment of the invention provides a method for filling sub-micron features on a substrate, comprising reactive precleaning the substrate, depositing a barrier layer on the substrate using high density plasma physical vapor deposition; depositing a seed layer over the barrier layer using high density plasma physical vapor deposition; and electro-chemically depositing a metal using a highly resistive electrolyte and applying a first current density during a first deposition period followed by a second current density during a second period.